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lxt331 dual t1/e1 line interface unit datasheet the lxt331 is a dual line interface unit (dliu) optimized for north america 1.544 mbps (t1) and international 2.048 mbps (e1/cept) applications. it features a constant low output impedance transmitter for high return loss. transmit pulse shape is selectable for various line lengths and cable types. the data recovery circuit also offers selectable slicer ratios for t1 or e1 applications. the lxt331 offers both a serial interface (sio) for microprocessor control and a hardware control mode for stand-alone operation. the lxt331 offers a variety of advanced diagnostic and performance monitoring features. it uses an advanced double-poly, double-metal cmos process and requires only a single 5-volt power supply. applications product features digital access and cross-connect systems (dacs) t1/e1 multiplexer sonet/sdh multiplexers digital loop carrier (dlc) terminals cost efficient afe for digital backend asics analog los using pmrk/nmrk complete line driver and data recovery functions constant low output impedance transmitter with a programmable equalizer that shapes pulses to meet the dsx-1 pulse template from 0 to 655 ft. high transmit and receive return loss meets or exceeds industry specifications including itu g.703 and ansi t1. 102- 1993 compatible with industry standard framers minimum receive signal of 500 mv, with selectable slicer levels (e1/dsx-1) to improve snr analog loopback function transmit performance monitors with driver fail monitor (dfm) output for transmit driver short circuit detection transmit driver performance monitor (dpm) output on external pins mtip and mring available in 44-pin plcc and 44-pin qfp packages as of january 15, 2001, this document replaces the level one document order number: 249074-001 lxt331 ? dual t1/e1 line interface unit . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt331 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 dual t1/e1 line interface unit ? lxt331 contents 1.0 pin assignments & signal descriptions .......................................................... 6 2.0 functional description ...........................................................................................10 2.1 receiver ..............................................................................................................10 2.2 transmitter ..........................................................................................................10 2.2.1 pulse shape ...........................................................................................11 2.2.2 driver performance monitor ...................................................................11 2.2.3 driver failure monitor.............................................................................12 2.3 control modes .....................................................................................................12 2.3.1 host mode control .................................................................................13 2.3.1.1 serial input word.......................................................................13 2.3.1.2 serial output word ....................................................................14 2.3.1.3 interrupt handling......................................................................14 2.3.2 hardware mode control .........................................................................14 2.4 diagnostic mode operation.................................................................................18 2.5 initialization & reset............................................................................................19 3.0 application information .........................................................................................20 3.1 power requirements...........................................................................................20 3.1.1 line interface requirements ..................................................................20 3.2 line protection ....................................................................................................21 3.2.1 1.544 mbps t1 applications ...................................................................21 3.2.2 2.048 mbps e1 coax applications .........................................................21 3.2.3 2.048 mbps e1 twisted-pair applications..............................................22 4.0 test specifications ..................................................................................................25 5.0 mechanical specifications ....................................................................................30
lxt331 ? dual t1/e1 line interface unit 4 datasheet figures 1 lxt331 block diagram ......................................................................................... 5 2 lxt331 44 pin assignments and markings .......................................................... 6 3 50% ami coding ................................................................................................. 11 4 lxt331 driver performance monitor .................................................................. 13 5 lxt331 sio write operations ............................................................................ 15 6 lxt331 sio read operation .............................................................................. 16 7 lxt331 interrupt handling .................................................................................. 17 8 transmit all ones data path............................................................................... 18 9 taos with analog loopback .............................................................................. 19 10 analog loopback ................................................................................................ 19 11 line interface for e1 coax ................................................................................. 22 12 typical lxt331 t1 application (host control mode, bipolar i/o) ....................... 23 13 typical lxt331 e1 120 w twisted pair application (hardware control mode) . 24 14 lxt331 transmit clock timing........................................................................... 27 15 lxt331 receive timing...................................................................................... 28 16 lxt331 serial input timing diagram .................................................................. 29 17 lxt331 serial output timing diagram ............................................................... 29 18 lxt331 plcc package specification................................................................. 30 19 lxt331 qfp package specification................................................................... 31 tables 1 pin descriptions .................................................................................................... 7 2 equalizer control inputs - hardware mode1 ....................................................... 12 3 sio input bit settings (see figure 5 ) .................................................................. 14 4 lxt331 serial data output bit coding ............................................................... 15 5 hardware mode diagnostic selection ................................................................. 18 6 recommended transmit transformer values .................................................... 20 7 transmit transformer combinations................................................................... 20 8 absolute maximum ratings ................................................................................ 25 9 recommended operating conditions ................................................................. 25 10 electrical characteristics (over recommended operating range) .................... 25 11 analog specifications (over recommended operating range) ......................... 26 12 lxt331 master clock and transmit timing characteristics (see figure 14 ) ..... 27 13 lxt331 receive characteristics (see figure 15 ) ............................................... 27 14 lxt331 serial i/o timing characteristics (see figure 16 and figure 17 ) .......... 28
dual t1/e1 line interface unit ? lxt331 datasheet 5 figure 1. lxt331 block diagram transceiver 1 equalizer tx - pll transmit monitor monitor analog loopback peak detector serial word transceiver 0 serial port len select taos enable line driver data slicers dfm dpm tclk tpos tneg pmrk nmrk mclk mtip mring ttip tring dfm rtip rring to transceiver 1 clke sclk sdi sdo aloop enable int ps transmit & timing control
lxt331 ? dual t1/e1 line interface unit 6 datasheet 1.0 pin assignments & signal descriptions figure 2. lxt331 44 pin assignments and markings package topside markings marking definition part # unique identifier for this product family. rev # identifies the particular silicon ? stepping ? ? refer to the specification update for additional stepping information. lot # identifies the batch. fpo # identifies the finish process order. aloop0/clke taos0/sclk len20/ps0 len10/int0 len00/gnd aloop1/sdi taos1/sdo mtip0 mring0 dpm0 rtip0 rring0 dfm0 rring1 rtip1 dpm1 mring1 mtip1 mclk gnd ttip0 tgnd0 tvcc0 tring0 len21/ps1 len11/int1 len01/spe dfm1 vcc ttip1 tgnd1 tvcc1 tring1 pmrk0 nmrk0 tneg0 tpos0 tclk0 trste tclk1 tpos1 tneg1 nmrk1 pmrk1 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 17 16 15 14 13 12 11 10 9 8 7 lxt331pe xx lxt331ph xxxxxx xxxxxxxx rev # part # part # lot # fpo # aloop0/clke taos0/sclk len20/ps0 len10/int0 len00/gnd aloop1/sdi taos1/sdo mtip0 mring0 dpm0 rtip0 rring0 dfm0 rring1 rtip1 dpm1 mring1 mtip1 mclk gnd ttip0 tgnd0 tvcc0 tring0 len21/ps1 len11/int1 len01/spe dfm1 vcc ttip1 tgnd1 tvcc1 tring1 pmrk0 nmrk0 tneg0 tpos0 tclk0 trste tclk1 tpos1 tneg1 nmrk1 pmrk1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1 lxt331qe xx LXT331QH xxxxxx xxxxxxxx rev # part # part # lot # fpo #
dual t1/e1 line interface unit ? lxt331 datasheet 7 table 1. pin descriptions pin plcc pin qfp symbol i/o 1 description 1 39 trste di tristate enable . forces all output pins to tri-state when held high and forces chip into reset mode. holds reset mode for 6 s after trste returns low. 2 40 tclk0 di transmit clock ? port 0 . 1.544 mhz for t1, 2.048 mhz for e1. the transmit data inputs are sampled on the falling edge of tclk. if tclk is pulled low, the transmit drivers are powered down and ttip and tring transmit outputs go to a high impedance state. 3 4 41 42 tpos0 tneg0 di di transmit positive and negative data, port 0 . these pins drive the positive and negative sides of the bipolar input pair for port 0. data to be transmitted onto the line is input at these pins. 5 6 43 44 nmrk0 pmrk0 do do receive negative and positive marks, port 0 . these pins are the data outputs from port 0. a signal on nmrk corresponds to receipt of a negative pulse on rtip/rring. a signal on pmrk corresponds to receipt of a positive pulse on rtip/rring. nmrk/ pmrk outputs are return-to-zero (rz). 71 clke di clock edge select (host mode) . when clke is high, sdo is valid on the rising edge of sclk.when clke is low, sdo is valid on the falling edge of sclk. aloop0 di analog local loopback enable, port 0 (hardware mode) . when aloop is high, the rtip/rring inputs from the port 0 twisted-pair line are disconnected and the transmit data outputs (ttip/tring) are routed back into the receiver. for normal operation, hold aloop low. 82 sclk di serial clock (host mode) . shifts data into or out of the serial interface register of the selected port. taos0 di transmit all ones enable, port 0 (hardware mode) . when taos is high, the tpos/tneg input is ignored and the selected port transmits a stream of ones at the tclk frequency. with no tclk, the mclk input becomes the transmit reference. for normal operation, hold taos low. refer to page 18 . 93 ps0 di port select, port 0 (host mode) . selects the serial interface registers of port 0. for each read or write operation, ps0 must transition from high to low, and remain low. len20 di line length equalizer 2, port 0 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 10 4 int0 do interrupt, port 0 (host mode) . goes low to flag the host processor that port 0 has changed state. int0 is an open drain output and must be tied to vcc through a resistor. len10 di line length equalizer 1, port 0 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 11 5 gnd di unused ( host mode) . must be tied to ground. len00 di line length equalizer 0, port 0 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 12 6 mclk di master clock. 1.544 mhz for t1, 2.048 mhz for e1. can be held low if tclk is present. 13 7 gnd s ground. ground return for vcc power supply. 14 8 ttip0 ao transmit tip, port 0 . the ttip and tring pins are differential driver outputs designed to drive a 35-200 ? load. line matching resistors and transformers can be selected to give the desired pulse height. 15 9 tgnd0 s ground, port 0 transmit driver. ground return for tvcc0 power supply. 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; s = po wer supply
lxt331 ? dual t1/e1 line interface unit 8 datasheet 16 10 tvcc0 s + 5 vdc power supply, port 0 transmit driver. tvcc0 must not vary from tvcc1 or vcc by more than 0.3 v. 17 11 tring0 ao transmit ring, port 0 . the ttip and tring pins are differential driver outputs designed to drive a 35-200 ? load. line matching resistors and transformers can be selected to give the desired pulse height. 18 19 12 13 mtip0 mring0 ai ai monitor tip and ring, port 0 . these pins monitor tip and ring outputs of either its own, or those of an adjacent lxt331 on the same board. if the application does not use this feature, tie one of these pins to a clock source and the other to a mid-level (referenced to the clock signal) voltage. the clock frequency can range from 100 khz to the tclk frequency. 20 14 dpm0 do driver performance monitor, port 0 . goes high to indicate the detection of 63 consecutive zeros. goes low upon the receipt of a one on the transmit monitor loop (mtip/mring). 21 22 15 16 rtip0 rring0 ai ai receive tip and ring, port 0 . rtip and rring comprise the receive line interface. this input pair should be connected to the line through a 1:1 transformer. 23 17 dfm0 do driver fail monitor, port 0 . goes high to indicate a driver output short condition. 24 25 18 19 rring1 rtip1 ai ai receive tip and ring, port 1 . refer to rring0 and rtip0 pins. 26 20 dpm1 do driver performance monitor , port 1 . refer to dpm0 pin. 27 28 21 22 mring1 mtip0 ai monitor tip and ring, port 1 . refer to mring0 and mtip0 pins. 29 23 tring1 ao transmit ring, port 1 . refer to tring0 pin. 30 24 tvcc1 s + 5 vdc power supply, port 1 transmit driver. tvcc1 must not deviate from tvcc0 or vcc by more than 0.3 v. 31 25 tgnd1 s ground, port 1 transmit driver. ground return for tvcc1 power supply. 32 26 ttip1 ao transmit tip, port 1 . refer to ttip0 pin. 33 27 vcc s + 5 vdc power supply input for all circuits except transmit drivers. 34 28 dfm1 do driver fail monitor, port 1 . refer to dfm0 pin. 35 29 spe di serial port enable (host mode) . spe must be clocked with mclk, tclk0 or tclk1 to enable host mode control through the serial port. len01 di line length equalizer 0, port 1 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 36 30 int1 do interrupt, port 1 (host mode). refer to int0 pin. len11 di line length equalizer 1, port 1 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 37 31 ps1 di port select, port 1 (host mode) . refer to ps0 pin. len21 di line length equalizer 2, port 1 (hardware mode) . determines the shape and amplitude of the transmit pulse. refer to table 2 on page 12 38 32 sdo do serial data output (host mode) . read data from the lxt331 registers are output on this pin. when clke is high, sdo is valid on the rising edge of sclk. when clke is low, sdo is valid on the falling edge of sclk. taos1 di transmit all ones enable, port 1 (hardware mode) . refer to taos0 pin. table 1. pin descriptions (continued) pin plcc pin qfp symbol i/o 1 description 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; s = po wer supply
dual t1/e1 line interface unit ? lxt331 datasheet 9 39 33 sdi di serial data input (host mode) . write data to the lxt331 registers are input on this pin. sdi is sampled on the rising edge of sclk. aloop1 di analog local loopback enable, port 1 (hardware mode) . refer to pin aloop0. 40 41 34 35 pmrk1 nmrk1 do do receive negative and positive marks, port 1 . refer to pmrk0 and nmrk0 pins. 42 43 36 37 tneg1 tpos1 di di transmit negative and positive data, port 1 . refer to tneg0 and tpos0 pins. 44 38 tclk1 di transmit clock, port 1 . refer to tclk0 pin. table 1. pin descriptions (continued) pin plcc pin qfp symbol i/o 1 description 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; s = po wer supply
lxt331 ? dual t1/e1 line interface unit 10 datasheet 2.0 functional description the lxt331 is a dual line interface unit (dliu), which contains two ports. refer to the simplified block diagram on page 1. the dliu is designed for both 1.544 mbps (dsx-1) and 2.048 mbps (e1) applications. both ports operate at the same frequency, which is determined by the tclk input. each port?s front end interfaces with two lines, one line for transmit, one line for receive. these two lines comprise a digital data loop for full-duplex transmission. each port?s back-end interfaces with a layer processor through bipolar data i/o channels. the dliu may either be controlled by a microprocessor via the serial port (host mode), or by hardwired pins for stand-alone operation (hardware mode). 2.1 receiver the two receivers in the lxt331 dliu are identical. the following paragraphs describe the operation of a single receiver. the input signal is received via a 1:1 transformer. the receiver requires fully differential inputs which are internally self-biased into 2.5 v. recovered data is output at pmrk and nmrk. refer to test specifications for receiver timing. the receive signal is processed through an adaptive peak detector and data slicers. the peak detector samples the received signal and determines its maximum value. a percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. for dsx-1 applications (line length inputs len0-len2 000 or 001), the threshold is set to 70% (typical) of the peak value. this threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. for e1 applications (len0-len2 = 000 or 001) the threshold is 50% (typical). the receiver is capable of accurately recovering signals with up to +13.6 db of attenuation (from 2.4 v), corresponding to a received signal level of approximately 500 mv. maximum line length is 1500 feet of abam cable (approximately 6 db of attenuation). regardless of received signal level, the peak detectors are held above a minimum level of 0.3 v (typical) to provide immunity from impulsive noise. built in pulse stretching circuitry maintains a minimum positive and negative mark pulse width (see table 13 and figure 15 on page 28 ). 2.2 transmitter the two transmitters in the lxt331 dliu are identical. the following paragraphs describe the operation of a single transmitter. transmit data is clocked serially into the device at tpos/tneg. input synchronization is supplied by the transmit clock (tclk). the tpos/tneg inputs are sampled on the falling edge of tclk. if tclk is held low, the transmitter remains powered down and the ttip/tring outputs are held in a high-z state (except in taos mode if mclk is available). each output driver is provided with
dual t1/e1 line interface unit ? lxt331 datasheet 11 a separate power supply pin (tvcc0 or tvcc1). current limiters on the output drivers provide short circuit protection. refer to test specifications for tclk timing characteristics. as shown in figure 3 , the lxt331 encodes transmit data using 50% alternate mark inversion (ami) line code. 2.2.1 pulse shape the transmitted pulse shape is determined by line length equalizer control signals len0 through len2. equalizer codes are hard-wired in hardware mode as shown in table 2 . in host mode, the len control codes are input through the serial interface. shaped pulses are applied to the ami line driver for transmission onto the line at ttip and tring. the line driver provides a constant low output impedance of < 3 ? (typical) regardless of whether it is driving marks or spaces or during transitions. this well-controlled impedance provides excellent return loss when used with external precision resistors (1% accuracy). see table 9 and table 10 for recommended transformer specifications, turns ratios, series resistor (rt) values, and typical return losses for various len codes. to minimize power consumption the dc blocking capacitor and the lxt331 can be connected directly to a 1:1.15 transformer without series resistors. pulses can be shaped for either 1.544 or 2.048 mbps applications. 1.544 mbps pulses for dsx-1 applications can be programmed to match line lengths from 0 to 655 feet of 22 awg abam cable. a combination of 9.1 ? resistors and a 1:2.3 transformer is recommended for maximum transmit return loss in dsx-1 applications. the lxt331 also matches fcc pulse mask specifications for csu applications. the lxt331 produces 2.048 mbps pulses for both 75 ? coaxial (2.37 v) or 120 ? shielded twisted-pair (3.0 v) lines through an output transformer with a 1:2 turns ratio. refer to the ? application information ? on page 20 for details on interface circuitry. 2.2.2 driver performance monitor the lxt331 incorporates a driver performance monitor (dpm) as shown in figure 4 on page 13 . the dpm output goes high on receipt of 63 consecutive zeros (at mtip and mring) and returns low on receipt of a transition. a reset command also drives the output signal low. the lxt331 uses its mtip and mring pins to monitor its own ttip and tring outputs or those of an adjacent chip. mark detection involves two criteria: 1. voltage threshold: a pulse must trip a threshold voltage above or below (depending on its polarity) the input bias voltage level. the lxt331 bias voltage is 2.5 v and the threshold for a mark is 2.5 0.79 v. figure 3. 50% ami coding bit cell ttip tring 10 1
lxt331 ? dual t1/e1 line interface unit 12 datasheet 2. pulse width: the monitor distinguishes between marks and noise pulses by the pulse width. lxt331 requires a mark pulse to be at least 120 ns wide (typical). as shown in figure 4 on page 13 , there are two type of marks: ? a ? and ? b ? . c1 and c2 detect ? a ? marks while the and gate (a1) ensures that both mark signals are present at the same time. if the pulse widths are adequate, i.e. both a positive mark on mtip and a negative mark on mring, the a1 output goes high. likewise c3 and c4 detect ? b ? marks. if the pulse meets the minimum width requirement, the and gate (a2) output goes high when there are both a negative mark on mtip and a positive mark on mring. the or gate (o1) passes the mark, as the signal ? zero ? , on to the clock/counter circuit which controls the dpm output. a latch samples the counter and goes high if the dpm circuit sees 63 consecutive zeros. any mark resets the counter. the dpm signal goes high after the 63 rd zero. 2.2.3 driver failure monitor the transceiver incorporates an internal driver failure monitor (dfm) that observes ttip and tring. driver failure is detected with a capacitor that is charged as a function of driver output current, and discharged as a measure of the maximum allowable current. shorted lines draw excess current, overcharging the cap. when the capacitor charge deviates outside the nominal charge window, a driver failure is reported. in host mode the dfm bit is set in the serial word. in both hardware and host modes the dfm pin goes high. during a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the dfm flag. 2.3 control modes the lxt331 transceiver operates in either standalone hardware mode (default) or host mode. in host mode a microprocessor controls the lxt331 via the serial i/o port (sio) which provides common access to both lius. in hardware mode, the transceiver is controlled through individual pins; a microprocessor is not required. table 2. equalizer control inputs - hardware mode 1 len2 len1 len0 line length 2 cable loss 3 application frequency low high high high high high low low high high high low high low high 0 - 133 ft abam 133-266 ft abam 266-399 ft abam 399-533 ft abam 533-655 ft abam 0.6 db 1.2 db 1.8 db 2.4 db 3.0 db dsx-1 1.544 mhz low low low low low high itu recommendation g.703 e1 - coax (75 ? ) e1 - twisted-pair (120 ? ) 2.048 mhz low high low fcc part 68, option a csu 1.544 mhz 1. len0-2 inputs are shown as high or low for hardware mode. for host mode serial inputs, high = 1 and low = 0. 2. line length from lxt331 to dsx-1 cross-connect point. 3. maximum cable loss at 772 khz.
dual t1/e1 line interface unit ? lxt331 datasheet 13 2.3.1 host mode control host mode is selected when a clock is applied to the spe pin. each of the two lius contains a pair of data registers, one for command inputs and one for status outputs. an sio transaction is initiated by a falling pulse on one of the two port select pins, ps0 or ps1 . only one liu can be selected at a time. a high-to-low transition on ps n is required for each subsequent access to the host mode registers. if both ps0 and ps1 are active simultaneously, port 0 has priority over port1. the liu addressed by the ps n pulse responds by writing the incoming serial word (at the sdi pin) into its command register. figure 5 on page 15 shows an sio write operation. the 16-bit serial word consists of an 8-bit command/address byte and an 8-bit data byte. if the command word contains a read request, the addressed liu subsequently outputs the contents of its status register onto the sdo pin. figure 6 on page 16 shows an sio read operation. the clock edge (clke) signal determines when the sdo output is valid (relative to sclk) as follows: if clke = high, sdo is valid on the rising edge of sclk. if clke = low, sdo is valid on the falling edge of sclk. refer to test specifications for sio timing. 2.3.1.1 serial input word figure 5 on page 15 shows the serial input data structure. the lxt331 is addressed by setting bit a4 in the address/command byte, corresponding to address 16. bit 1 of the serial address/ command byte provides read/write (r/w) control when the chip is accessed. the r/w bit is set to logic 1 to read the data output byte from the chip, and set to logic 0 to write the input data byte to the chip. the second 8 bits of a write operation (the data input byte) clear the driver performance monitor (dpm) and driver fail monitor (dfm) interrupts, reset the chip, and control diagnostic modes. the first and second bits (d0-1) clear and/or mask the dpm and dfm interrupts, and the last 3 bits (d5-7) control operating modes (normal and diagnostic) and chip reset. refer to table 3 for details on bits d5-7. figure 4. lxt331 driver performance monitor pulse width monitor pulse width monitor pulse width monitor pulse width monitor + + + + - - - - mtip mring +2.5 v +790 mv +2.5 v -790 mv c1 c2 c3 c4 a1 a2 o1 clk cntr63 zero* dpm i c r r osq a b
lxt331 ? dual t1/e1 line interface unit 14 datasheet 2.3.1.2 serial output word figure 6 shows the serial output data structure. sdo is high impedance when sdi receives an address/command byte. if sdi receives a write command (r/w = 0), sdo remains in high impedance. if the command is a read (r/w = 1), then sdo becomes active after the last command/ address bit (a6) and remains active for eight sclk cycles. typically the first bit out of sdo changes the state of sdo from high z to a low/high. this occurs approximately 100 ns after the eighth following edge of sclk. the output data byte reports dpm and dfm conditions, equalizer settings, and operating modes (normal or diagnostic). the first 5 bits (d0-4) report dpm and dfm status and the line length equalizer settings. the last 3 bits (d5-7) report operating modes and interrupt status as defined in table 4 . if the int line for the respective port is high (no interrupt is pending), bits d5-7 report the operating modes listed in table 4 . if the int line for the respective port is low, the interrupt status overrides all other reports and bits d5-7 reflect the interrupt status as listed in table 4 . 2.3.1.3 interrupt handling the host mode provides two latched interrupt output pins, int0 and int1 , one for each liu. an interrupt is triggered by a change in the dpm or dfm bit (d0=dpm, d1=dfm). as shown in figure 7 on page 17 , either or both interrupt generators can be masked by writing a 1 to the corresponding bit (d0 or d1) of the input data byte. when an interrupt occurrs, the int output pin is pulled low. the output stage of each int pin consists of a pull-down device; thus an external pull-up resistor is required. clear the interrupts as follows: 1. if one or both interrupt bits (dpm or dfm of the output data byte) are high, write a 1 to the corresponding bit of the input data byte to clear the interrupt. leave a 1 in either bit position to effectively mask that interrupt. to re-enable the interrupt capability, reset either d0 or d1 or both to 0. 2. if neither dpm nor dfm is high, reset the chip to clear the interrupt. to reset the chip, set data input bits d5 and d6 = 1, and d7 = 0. 2.3.2 hardware mode control hardware control is the default operating mode. the lxt331 operates in hardware mode unless a clock is applied to the len21/spe pin. in hardware mode, the sio pins are re-mapped to provide control functions. in hardware mode, the pmrk/nmrk outputs are valid on the rising edge of rclk. table 3. sio input bit settings (see figure 5 ) mode tst bit d5 aloop bit d6 taos bit d7 analog loopback 0 1 0 transmit all ones 0 x 1 reset/high z 1 1 0
dual t1/e1 line interface unit ? lxt331 datasheet 15 table 4. lxt331 serial data output bit coding bit d5 bit d6 bit d7 operating modes 0 0 0 reset has occurred, or no program input (i.e. normal operation). 0 0 1 taos active 0 1 0 aloop active 0 1 1 taos and aloop active bit d5 bit d6 bit d7 interrupt status 1 0 1 dfm has changed state since the last clear dfm occurred 1 1 0 dpm has changed state since the last clear dpm occurred 1 1 1 dpm and dfm have changed state since the last clear dpm and dmf occurred figure 5. lxt331 sio write operations ps n sclk sdi input data byte d0 d1 d2 d3 d4 d5 d6 d7 r/w a0 a1 a2 a3 a4 a5 a6 address/command byte data input/output byte address/ command byte sdo* * sdo - remains high impedence r/w = 1 : read r/w = 0 : write set operation mode or reset 0 r/w 0 1 x a0 0 0 0 0 a6 x = don ? t care dpm d0 (lsb) 1 = clear dfm clear/mask interrupt 1 = clear len0 len1 len2 tst 0 = normal ops d7 (msb) taos 1 = enable aloop 1 = enable
lxt331 ? dual t1/e1 line interface unit 16 datasheet figure 6. lxt331 sio read operation ps n sclk sdi output data byte address/command byte data output byte operating modes or interrupt status 1 r/w 0 a1 0 0 0 1 a4 0 x a6 x = don ? t care d7 high impedance d0 d1 d2 d3 d4 d5 d6 sdo don ? t care performance monitor line length equalizer setting dpm taos d0 (lsb) d7 (msb) dfm len0 len1 len2 tst aloop 1 = true 0 = normal 1 = enabled 1 = enabled 1 = true
dual t1/e1 line interface unit ? lxt331 datasheet 17 figure 7. lxt331 interrupt handling mask interrupts ? mask which interrupts ? does an interrupt condition exist ? read output status word* (bits d5-d7=operating mode) (no interrupt) int = high no read output status word* (bits d5-d7=interrupt status) int = low (interrupt) yes are both interrupt conditions masked ? no yes no read output status word* (bits d5-d7=operating mode) write "1" to d0 of input status word to mask dpm interrupt write "1 1" to d0-d1 of input status word to mask dpm & dfm interrupt write "1" to d1 of input status word to mask dfm interrupt yes int goes high what interrupt condition exists ? write "1" to d0 of input status word to re-enable dpm interrupt write "1 1" to d0-d1 of input status word to re-enable dpm & dfm interrupt write "1" to d1 of input status word to re-enable dfm interrupt write "0" to d0 of input status word to re-enable dpm interrupt write "0 0" to d0-d1 of input status word to re-enable dpm & dfm interrupts write "0" to d1 of input status word to re-enable dfm interrupt re-enable which interrupts ? re-enable interrupts ? dfm dpm dpm & dfm *regardless of interrupt status, bit d0 indicates dpm status d1 indicates dpm status and d2 - d7 indicate len status *regardless of interrupt status, bit d0 indicates dpm status, d1 indicates dpm status and d2 - d4 indicate len status dfm dpm dfm and dpm no yes dfm dpm dfm and dpm start-up or restart interrupts enabled
lxt331 ? dual t1/e1 line interface unit 18 datasheet 2.4 diagnostic mode operation the lxt331 offers two diagnostic modes. analog loopback (aloop) and transmit all ones (taos) are available under both host and hardware control modes. in host mode, diagnostic modes are selected by writing the appropriate sio bits. in hardware mode, diagnostic modes are selected by a combination of pin settings. the pins must be held at the specified levels for a minimum of 20 ns (typically). table 5 lists hardware mode control settings for the various diagnostic modes. transmit all ones. see figure 8 . transmit all ones (taos) is selected when taos = 1. in taos mode the tpos and tneg inputs are ignored, but the transmitter remains locked to the tclk input. when taos is selected, the transceiver transmits a continuous stream of 1s at the tclk frequency. if tclk is not supplied, mclk is used as the transmit reference. taos and analog loopback can be selected simultaneously as shown in figure 9 . analog loopback. see figure 10 . analog loopback (aloop) is selected when aloop = 1. in aloop mode the receive line input (rtip/rring) is blocked. the transmit outputs (ttip and tring) are looped back through the receiver input and output at pmrk and nmrk. the transmitter circuits are unaffected by aloop. transmitting onto an improperly terminated line may produce unexpected pulse widths at pmrk and nmrk. reset / tri-state . by holding the trste pin high for at least 200 ns, all output drivers (both digital and analog) go to the high z state and the chip logic is reset. the reset/high z state is maintained for 6 s after trste returns low. table 5. hardware mode diagnostic selection mode lxt331 pin trste aloop taos analog loopback l h l transmit all ones l x h reset/high z h x x figure 8. transmit all ones data path ttip (all 1s) timing & control taos tclk tpos tneg ttip tring rtip rring transmit all ones = aloop 0 taos 1 pmrk nmrk
dual t1/e1 line interface unit ? lxt331 datasheet 19 2.5 initialization & reset upon initial power up, the transceiver is held static until the power supply reaches approximately 3 v. upon crossing this threshold, the device clears all internal registers. tclk is the transmit reference, and mclk is the bias reference. the plls are continuously calibrated. the transceiver can be reset from the host or hardware mode. in host mode, reset is commanded by writing 1s to tst and aloop, and a 0 to taos (bits d5, d6 and d7, respectively, of the sio input data byte). in either mode, reset is commanded by holding the trste pin high for approximately 200 ns. all output signals are tri-stated at this time. in hardware mode, the falling edge of trste initiates reset for the entire chip. host mode resets the selected port sio registers to 0. reset is not generally required for the port to be operational. figure 9. taos with analog loopback figure 10. analog loopback (all 1s) timing & control ttip tring rtip rring transmit all ones = aloop 1 taos 1 pmrk nmrk with aloop taos tclk tpos tneg timing & control ttip tring rtip rring analog loopback aloop 1 taos 0 pmrk nmrk tclk tpos tneg
lxt331 ? dual t1/e1 line interface unit 20 datasheet 3.0 application information 3.1 power requirements the lxt331 is a low-power cmos device. three separate power pins are provided: one pin for each port ? s transmitter circuits (tvcc0 and tvcc1) and a pin for all remaining circuits (vcc). the lxt331 typically operates from a single +5 v power supply that is tied to all three vcc inputs. note that all power pins must be within 0.3 v of each other, and decoupled to their respective grounds separately. isolation between the transmit and receive circuits is provided internally. during normal operation or analog loopback, the transmitter powers down when tclk is not supplied. 3.1.1 line interface requirements table 6 lists transformer values for 1.544 mbps and 2.048 mbps applications. table 7 shows combinations of transformers, series resistors and the len control settings that produce a variety of return loss values. table 6. recommended transmit transformer values parameter value turns ratio (t1) 1:2/1:1.15/1:2.3 (tx)/ 1:1 (rx) turns ratio (e1) 1:2 (tx) / 1: 1 (rx) primary inductance 1.2 mh minimum leakage inductance 0.5 ? maximum interwinding capacitance 25 pf maximum dc resistance (primary) 1 ? maximum et (breakdown voltage) 1 kv minimum table 7. transmit transformer combinations len xfmr ratio 1 rt value 2 rtn loss 3 for t1/dsx-1 100 ? twisted-pair applications: 011-111 1:2 rt = 9.1 ? 14db 011-111 1:2.3 rt = 9.1 ? 18db 011-011 1:1.15 rt = 0 ? 1db for e1 120 ? twisted-pair applications: 001 1:2 rt = 15 ? 18db 000 1:2 rt = 9.1 ? 10db 1. transformer turns ratio accuracy is 2%. 2. rt values are 1%. 3. typical return loss, 51khz - 3.072 mhz band, with a capacitor in parallel with the primary side of the transformer.
dual t1/e1 line interface unit ? lxt331 datasheet 21 3.2 line protection on the receive side, 1 k ? series resistors protect the receiver against current surges coupled into the device. due to the high receiver impedance (40 k ? typical) the resistors do not affect the receiver sensitivity. on the transmit side, schottky diodes d1-d4 protect the output driver. while not mandatory for normal operation, these protection elements are strongly recommended to improve the design ? s robustness. 3.2.1 1.544 mbps t1 applications figure 12 on page 23 shows a typical host mode t1 application. the serial interface pins are grouped at the top. host mode is selected by applying clock (mclk or tclk ) to the spe pin. when the trste pin (shown at lower left) is pulled low, the lxt331 operates normally. pulling this pin high causes all outputs to go to a high impedance state. figure 12 on page 23 also shows a dual framer that recovers the clock from pmrk and nmrk. the dfm and dpm monitor output signals are available to drive optional external circuits. the transmitter power supply pins are tied to the common +5 vdc bus. note that 68 f decoupling capacitors are installed. the power supply for the remaining (non-driver) circuitry includes 1.0 f and 0.1 f decoupling capacitors. note that all vcc pins must be within 0.3 v of each other. the line interface circuitry is identical for both liu ports. the precision resistors, in line with the transmit transformer, provide optimal return loss. the recommended transformer/resistor combinations (on the transmit side) are listed in table 7 . 1:1 transformers are used on the receive side. 3.2.2 2.048 mbps e1 coax applications figure 11 shows the line interface for a typical 2.048 mbps e1/cept coaxial (75 ? ) application. the len code should be set to 000 for coax. with 9.1 ? rt resistors in line with 1:2 output transformers, the lxt331 produces 2.37 v peak pulses as required for coax applications. for e1 75 ? coaxial applications: 001 1:2 rt = 14.3 ? 10db 000 1:2 rt = 9.1 ? 18db table 7. transmit transformer combinations len xfmr ratio 1 rt value 2 rtn loss 3 for t1/dsx-1 100 ? twisted-pair applications: 1. transformer turns ratio accuracy is 2%. 2. rt values are 1%. 3. typical return loss, 51khz - 3.072 mhz band, with a capacitor in parallel with the primary side of the transformer.
lxt331 ? dual t1/e1 line interface unit 22 datasheet 3.2.3 2.048 mbps e1 twisted-pair applications figure 13 shows a typical 2.048 mbps e1 twisted-pair (120 ? ) application. the line length equalizers are controlled by the hardwired len inputs. with the len code set to 001 and 15 ? rt resistors in line with the 1:2 output transformers, the lxt331 produces the 3.0 v peak pulses required for twisted-pair applications. figure 11. line interface for e1 coax lxt331 ttip n tring n rtip n rring n 1:2 1:1 rt rt 470pf 75 ? 1k ? 1k ? 1 vcc d2 d1 vcc d4 d3 2 typical value, adjust for board parasitics to obtain optimum return loss. 1 d1, d2, d3 & d4 are protection diodes (schottky) international rectifier: 11dq04 or 10bq060; motorola: mbr0540t1. 2
dual t1/e1 line interface unit ? lxt331 datasheet 23 figure 12. typical lxt331 t1 application (host control mode, bipolar i/o) 1.544 mhz clock soure dual framer +5v lxt331 mclk trste tclk0 pmrk0 tneg0 nmrk0 tpos0 tpos1 tclk1 tneg1 pmrk1 nmrk1 dpm1 dfm1 dpm0 dfm0 ttip0 tring0 rtip0 rring0 vcc gnd 1:1 rt 100 ? 0.1 f rtip1 rring1 ttip1 tring1 mring0 mtip0 mring1 mtip1 1 f tvcc0 tgnd0 tvcc1 tgnd1 sdi sdo clke sclk ps1 to/from p / controller +5 v +5 v 68 f 68 f int1 int0 1:n 470 pf rt see inset for circuit inset vcc d4 d3 vcc d2 d1 ttipx tringx 1 1 2 1k ? 1k ? 1:1 100 ? 1k ? 1k ? 1:n 470 pf rt see inset for circuit rt 2 1 1 2 refer to table 6 for transformer specifications. typical value. adjust capacitor value for board parasitics to obtain optimum return loss. 1 1. transformer turns ratio accuracy is 2%. 2. refer to table 7 for rt values. 3. typical return loss, 51 khz - 3.072 mhz band. 4. d1, d2, d3 & d4 are protection diodes (schottky) international rectifier: 11dq04 or 10bq060; motorola: mbr0540t1. notes: spe ps0 normal high-z
lxt331 ? dual t1/e1 line interface unit 24 datasheet figure 13. typical lxt331 e1 120 ? twisted pair application (hardware control mode) +5v 1:1 rt 120 ? 0.1 f 1 f 1:n 470 pf rt see inset for circuit 1 1 2 1k ? 1k ? 1:1 120 ? 1k ? 1k ? 1:n 470 pf rt see inset for circuit rt 2 1 1 dual framer 2.048 mhz clock source +5v lxt331 mclk trste tclk0 pmrk0 tneg0 nmrk0 tpos0 tpos1 tclk1 tneg1 pmrk1 nmrk1 dpm1 dfm1 dpm0 dfm0 ttip0 tring0 rtip0 rring0 vcc gnd rtip1 rring1 ttip1 tring1 mring0 mtip0 mring1 mtip1 len01 len11 len21 taos1 tvcc1 tgnd1 aloop1 len00 len10 len20 taos0 tvcc0 tgnd0 aloop0 68 f 68 f +5v normal high-z inset vcc d4 d3 vcc d2 d1 ttipx tringx 2 refer to table 6 for transformer specifications. typical value. adjust capacitor value for board parasitics to obtain optimum return loss. 1 1. transformer turns ratio accuracy is 2%. 2. refer to table 7 for rt values. 3. typical return loss, 51 khz - 3.072 mhz band. 4. d1, d2, d3 & d4 are protection diodes (schottky) international rectifier: 11dq04 or 10bq060; motorola: mbr0540t1. notes:
dual t1/e1 line interface unit ? lxt331 datasheet 25 4.0 test specifications note: the minimum and maximum values in table 8 through table 14 and figure 14 through figure 17 represent the performance specifications of the lxt331 and are guaranteed by test, except where noted by design. table 8. absolute maximum ratings parameter sym min max unit dc supply (referenced to gnd) vcc, tvcc0, tvcc1 -0.3 6.0 v input voltage, any pin 1 v in gnd - 0.3 vcc + 0.3 v input current, any pin 2 i in -10 10 ma storage temperature t st -65 150 c caution: operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed or implied at these extremes. 1. excluding rtip and rring which must stay within - 6 v to vcc + 0.3 v. 2. transient currents of up to 100 ma will not cause scr latch-up. ttip0 & 1, tring0 & 1, vcc, tvcc0 & 1 and tgnd0 & 1 can withstand continuous current of 100 ma. table 9. recommended operating conditions parameter symbol minimum typical 1 maximum unit dc supply 2 vcc, tvcc0, tvcc1 4.75 5.0 5.25 v lxt331pe & qe ambient operating temperature t a -40 25 85 c lxt331ph & qh ambient operating temperature t a -5 25 85 c 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. variation between tvcc0, tvcc1 and vcc must be less than 0.3 v. table 10. electrical characteristics (over recommended operating range) parameter sym min typ 1 max unit test conditions total power dissipation - t1 2 (maximum line length, 75 ? load) pp - 550 680 mw -40 to +85 c pd - 550 650 mw 0 to +85 c total power dissipation - t1 3 (maximum line length, 43 ? load) pp - 775 1000 mw -40 to +85 c pd - 775 980 mw 0 to +85 c total power dissipation - e1 2 pd - 380 520 mw 100% ones density 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. 100% 1s density and maximum line length. driving a line load over operating temperature range. includes device and load. digital input levels are within 10% of the supply rails. digital outputs are driving a 50 pf capacitive load. 3. 100% 1s density and maximum line length. driving a line load (corresponding to rt value of 9.1 ? and 1:2 transformer ratio) over operating range. include device and load. digital input levels are within 10% of the supply rails. digital outputs are dri ving a 50 pf capacitive load. 4. functionality of pins depends on mode. 5. output drivers will output cmos logic levels into cmos loads. 6. all digital input pins. 7. for mtip0, mring0, mtip1 and mring1.
lxt331 ? dual t1/e1 line interface unit 26 datasheet high level input voltage 4,5 vih 2.0 - - v low level input voltage 4,5 vil - - 0.8 v high level output voltage 4,5 voh 2.4 - - v iout = - 400 ? low level output voltage 4,5 vol - - 0.4 v iout = 1.6 ma input leakage current 6 illd 0 - 10 a input leakage current 7 illm 0 - 50 a three-state leakage current 4 isl - - 10 a ttip/tring leakage current itr - - 1.2 ma in power down and tri-state table 11. analog specifications (over recommended operating range) parameter min typ 1 max unit test conditions ami output pulse amplitudes dsx-1 2.4 3.0 3.6 v measured at the dsx e1 (120 ?) 2.7 3.0 3.3 v measured at line side e1 (75 ?) 2.13 2.37 2.61 v measured at line side transmit amplitude variation with supply 3 -12.5% recommended output load at ttip and tring - 75 - ? driver output impedance 3 -310 ? @ 772 khz jitter added by the transmitter 2 10 hz - 8khz 3 - 0.005 0.01 ui t1 jitter bands 8 khz - 40 khz 3 - 0.015 0.025 ui 10 hz - 40 hz 3 - 0.02 0.025 ui broad band - 0.03 0.05 ui jitter added by the transmitter 2 20 hz - 100 khz - - 0.05 ui e1 jitter band output power levels 3 dsi 2 khz bw @ 772 khz 12.6 - 17.9 dbm @ 1544 khz -29 - - db positive-to-negative pulse imbalance - - 0.5 db differential input impedance - 40 - k ? sensitivity below dsx (0 db = 2.4 v) (max 6 db cable attenuation) 13.6 - - db 500 - - mv 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. input signal at tclk is jitter-free. 3. not production tested, but guaranteed by design and other correlation methods. table 10. electrical characteristics (over recommended operating range) parameter sym min typ 1 max unit test conditions 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. 100% 1s density and maximum line length. driving a line load over operating temperature range. includes device and load. digital input levels are within 10% of the supply rails. digital outputs are driving a 50 pf capacitive load. 3. 100% 1s density and maximum line length. driving a line load (corresponding to rt value of 9.1 ? and 1:2 transformer ratio) over operating range. include device and load. digital input levels are within 10% of the supply rails. digital outputs are dri ving a 50 pf capacitive load. 4. functionality of pins depends on mode. 5. output drivers will output cmos logic levels into cmos loads. 6. all digital input pins. 7. for mtip0, mring0, mtip1 and mring1.
dual t1/e1 line interface unit ? lxt331 datasheet 27 peak detector squelch level - 226 - mv data decision threshold dsx-1 63 70 77 % peak e1 43 50 57 % peak table 12. lxt331 master clock and transmit timing characteristics (see figure 14 ) parameter sym min typ 1 max unit master clock frequency dsx-1 mclk - 1.544 - mhz e1 mclk - 2.048 - mhz master clock tolerance mclkt - 50 - ppm master clock duty cycle mclkd 10 - 90 % transmit clock frequency dsx-1 tclk - 1.544 - mhz e1 tclk - 2.048 - mhz transmit clock tolerance tclkt - 50 - ppm transmit clock duty cycle tclkd 10 - 90 % tpos/tneg to tclk setup time tsut 25 - - ns tclk to tpos/tneg hold time tht 25 - - ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 14. lxt331 transmit clock timing table 13. lxt331 receive characteristics (see figure 15 ) parameter sym min typ 1 max unit test conditions pmrk/nmrk pulse width t1 tmpw - 324 - ns e1 tmpw - 244 - ns receiver throughput delay trxd - 65 - ns 3.0 v pulse 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 11. analog specifications (over recommended operating range) (continued) parameter min typ 1 max unit test conditions 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. input signal at tclk is jitter-free. 3. not production tested, but guaranteed by design and other correlation methods. t sut t ht tclk tpos tneg
lxt331 ? dual t1/e1 line interface unit 28 datasheet figure 15. lxt331 receive timing table 14. lxt331 serial i/o timing characteristics (see figure 16 and figure 17 ) parameter sym min typ 1 max unit test conditions rise/fall time - any digital output trf - - 100 ns load 1.6 ma, 50pf sdi to sclk setup time tdc 50 - - ns sclk to sdi hold time tcdh 50 - - ns sclk low time tcl 240 - - ns sclk high time tch 240 - - ns sclk rise and fall time tr, tf - - 50 ns ps to sclk setup time tpc 50 - - ns sclk to ps hold time tcph 50 - - ns ps inactive time tpwh 250 - - ns sclk to sdo valid tcdv - - 200 ns 16th sclk falling edge or ps rising edge to sdo high z tcdz - 100 - ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. rtip rring nmark pmark trxd tmpw tmpw trxd
dual t1/e1 line interface unit ? lxt331 datasheet 29 figure 16. lxt331 serial input timing diagram figure 17. lxt331 serial output timing diagram tpwh tcph tcl tch tpc sclk sdi tdc lsb tcdh lsb tcdh msb control byte data byte ps sclk tcdz tcdz high z high z tcdv tcdv sdo clke=1 sdo clke=0 ps
lxt331 ? dual t1/e1 line interface unit 30 datasheet 5.0 mechanical specifications figure 18. lxt331 plcc package specification a 2 a d f a 1 c b d 1 d c l plastic lead chip carrier (plcc) part number lxt331pe temperature range -40 c to + 85 c part number lxt331ph temperature range -5 c to + 85 c 44-pin plcc dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 ? 1.270 ? c 0.026 0.032 0.660 0.813 d 0.685 0.695 17.399 17.653 d 1 0.650 0.656 16.510 16.662 f 0.013 0.021 0.330 0.533
dual t1/e1 line interface unit ? lxt331 datasheet 31 figure 19. lxt331 qfp package specification a 1 a 2 l a b l 1 d d 1 e d 3 e 1 e 3 for sides with even number of pins e / 2 for sides with odd number of pins e 3 3 quad flat pack part number lxt331qe temperature range -40 c to + 85 c part number LXT331QH temperature range -5 c to + 85 c 44-pin qfp dim inches millimeters min max min max a ? 0.096 ? 2.45 a1 0.010 ? 0.25 ? a2 0.077 0.083 1.95 2.10 b 0.012 0.018 0.30 0.45 d 0.510 0.530 12.95 13.45 d1 0.390 0.398 9.90 10.10 d3 0.315 bsc 1 (nominal) 8.00 bsc 1 (nominal) e 0.510 0.530 12.95 13.45 e1 0.390 0.398 9.90 10.10 e3 0.315 bsc 1 (nominal) 8.00 bsc 1 (nominal) e 0.031 bsc 1 (nominal) 0.80 bsc 1 (nominal) l 0.029 0.041 0.73 1.03 l1 0.063 ref (nominal) 1.60 ref (nominal) q3 5 16 5 16 q0 7 0 7 1. bsc ? basic spacing between centers

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